1. Field of the Invention
This invention relates to processors and, more particularly, to implementation of cache memory systems.
2. Description of the Related Art
To improve execution performance, processors commonly include multiple levels of caches. For example, a processor may include a fast first-level (L1) cache backed by a larger, slower second-level (L2) cache. Such an arrangement may reduce average memory access latency relative to an implementation in which the L2 cache is omitted, in that an L1 cache miss that hits in the L2 cache need not incur the full latency of an access to system memory.
The integration of multiple processor cores into a single processor has resulted in configurations in which several independent L1 caches within the cores may share a common L2 cache. Depending on the configuration of the caches, certain memory activity that occurs with respect to the L2 cache may necessitate invalidation of data in each of the L1 caches. For example, if an L2 cache line is invalidated, it may be necessary to invalidate any lines resident in the L1 caches that correspond to the invalidated L2 cache line.
However, the state of the data to be invalidated may differ among the various L1 caches. For example, the data may not exist in some L1 caches, while in others, it may reside in different locations of the cache (e.g., in different cache ways). Correspondingly, it may be necessary to determine and communicate invalidation information separately for each processor core. As the number of cores increases, however, the complexity of routing an increased amount of invalidation information between the lower-level cache and the cores may increase processor implementation costs, in terms of factors such as die area and power consumption.